Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same

ABSTRACT

It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q 1  and a PMOS transistor Q 2  which are formed in an NMOS formation region A 1  and a PMOS formation region A 2  respectively have P −  pocket regions  17  and N −  pocket regions  27  in vicinal regions of extension portions  14   e  and  24   e  of N +  source-drain regions  14  and P +  source-drain regions  24 , respectively. On the other hand, an N-type variable capacitance C 1  and a P-type variable capacitance C 2  which are formed in an N-type variable capacitance formation region A 3  and a P-type variable capacitance formation region A 4  respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P −  pocket regions  17  and the N −  pocket regions  27.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device having aninsulated gate type transistor and an insulated gate type capacitanceand a method of manufacturing the semiconductor device.

[0003] 2. Description of the Background Art

[0004] In a transistor having a gate length of a subquarter micron orless, a pocket injecting process for forming pocket regions is executedin order to suppress a short channel effect. The pocket injection isalso referred to as NUDC (Non Uniformly Doped Channel).

[0005]FIG. 36 is a sectional view showing the pocket injecting process.As shown in FIG. 36, in the formation of a CMOS transistor, an NMOSformation region A11 and a PMOS formation region A12 are isolated fromeach other through an isolating film 102 provided in an upper layerportion of a semiconductor substrate 101.

[0006] In the NMOS formation region A11, a gate oxide film 112 and agate electrode 113 are formed on a surface of a P well region 111 and aP-type impurity ion 103 is implanted and diffused by using the gateelectrode 113 as a mask. Consequently, a P-type impurity implantationregion 119 to be pocket regions of an NMOS transistor is formed.

[0007] In the PMOS formation region A12, similarly, a gate oxide film122 and a gate electrode 123 are formed on a surface of an N well region121 and an N-type impurity ion 104 is implanted and diffused by usingthe gate electrode 123 as a mask. Consequently, an N-type impurityimplantation region 129 to be pocket regions of a PMOS transistor isformed.

[0008] More specifically, in the pocket injecting process, an impurityof the same conductivity type as that of a channel region of each MOStransistor is implanted into each of the NMOS formation region A11 andthe PMOS formation region A12. In the pocket injecting process, thedistribution of an impurity in a direction of a channel length becomesnonuniform and an effective channel impurity concentration is increasedwhen a gate length becomes smaller. As a result, it is possible tosuppress the short channel effect.

[0009]FIG. 37 is a sectional view showing a state in which a CMOStransistor is finished after the pocket injecting process.

[0010] As shown in FIG. 37, in the NMOS formation region A11, N⁺source-drain regions 114 and 114 are formed to interpose a channelregion provided under the gate electrode 113 and tip regions opposed toeach other between the N⁺ source-drain regions 114 and 114 are extensionportions 114 e, respectively.

[0011] In a vicinal region of the extension portion 114 e, the P-typeimpurity implantation region 119 remains as P⁻ pocket regions 117 fromthe extension portion 114 e to a part of the channel region. Moreover,side walls 116 and 116 are formed on both side surfaces of the gateelectrode 113, respectively.

[0012] Thus, an NMOS transistor Q11 is formed by the gate oxide film112, the gate electrode 113, the N⁺ source-drain regions 114, the sidewall 116 and the P⁻ pocket regions 117.

[0013] In the PMOS formation region A12, P⁺ source-drain regions 124 and124 are formed to interpose a channel region provided under the gateelectrode 123 and tip regions opposed to each other between the P⁺source-drain regions 124 and 124 are extension portions 124 e,respectively.

[0014] In a vicinal region of the extension portion 124 e, the N-typeimpurity implantation region 129 remains as N⁻ pocket regions 127 fromthe extension portion 124 e to a part of the channel region. Moreover,side walls 126 and 126 are formed on both side surfaces of the gateelectrode 123, respectively.

[0015] Thus, a PMOS transistor Q12 is formed by the gate oxide film 122,the gate electrode 123, the P⁺ source-drain regions 124, the side wall126 and the N⁻ pocket regions 127.

[0016] On the other hand, in a high-frequency analog circuit or ahigh-speed digital circuit, it is necessary to manufacture an LC typeVCO (Voltage Controlled Oscillator) by using an inductor (L) and avariable capacitance (C).

[0017] In the case in which the variable capacitance to be an insulatedgate type capacitance which has a small loss is to be obtained byutilizing the structure of the MOS transistor, it is necessary togenerate an accumulation type variable capacitance in which impuritiesin a substrate (a body region) and extraction electrode portions havethe same conductivity type.

[0018]FIG. 38 is a sectional view showing a structure of theaccumulation type variable capacitance. As shown in FIG. 38, in theformation of the accumulation type variable capacitance, a P-typevariable capacitance formation region A13 and an N-type variablecapacitance formation region A14 are isolated from each other through anisolating film 102 provided in an upper layer portion of a semiconductorsubstrate 101.

[0019] In the P-type variable capacitance formation region A13, P⁺extraction electrode regions 134 and 134 are formed to interpose achannel region provided under a gate electrode 133 and tip regionsopposed to each other between the P⁺ extraction electrode regions 134and 134 are extension portions 134 e, respectively.

[0020] In a vicinal region of the extension portion 134 e, N⁻ pocketregions 137 are formed from the extension portion 134 e to a part of thechannel region. Moreover, side walls 136 and 136 are formed on both sidesurfaces of the gate electrode 133, respectively.

[0021] Thus, a P-type variable capacitance C11 is formed by a gate oxidefilm 132, the gate electrode 133, the P⁺ extraction electrode regions134, the side wall 136 and the N⁻ pocket regions 137. In other words,the P-type variable capacitance C11 acts as an insulated gate typecapacitance in which the P⁺ extraction electrode regions 134 are set toone of electrodes, the gate electrode 133 is set to the other electrodeand the gate oxide film 132 is set to an interelectrode insulating film.

[0022] In the N-type variable capacitance formation region A14, N⁺extraction electrode regions 144 and 144 are formed to interpose achannel region provided under a gate electrode 143 and tip regionsopposed to each other between the N⁺ extraction electrode regions 144and 144 are extension portions 144 e, respectively.

[0023] In a vicinal region of the extension portion 144 e, P⁻ pocketregions 147 are formed from the extension portion 144 e to a part of thechannel region. Moreover, side walls 146 and 146 are formed on both sidesurfaces of the gate electrode 143, respectively.

[0024] Thus, an N-type variable capacitance C12 is formed by a gateoxide film 142, the gate electrode 143, the N⁺ extraction electroderegions 144, the side wall 146 and the P⁻ pocket regions 147. In otherwords, the N-type variable capacitance C12 acts as an insulated gatetype capacitance in which the N⁺ extraction electrode regions 144 areset to one of electrodes, the gate electrode 143 is set to the otherelectrode and the gate oxide film 142 is set to an interelectrodeinsulating film.

[0025]FIGS. 39 and 40 are views illustrating a degree of a change in acapacitance value of the N-type variable capacitance C12. In the case inwhich a gate voltage VG to be applied to the gate electrode 143 is lowerthan 0 V, a depletion layer 148 is extended downward in an N well region121 provided under the gate electrode 143 as shown in FIG. 39 so that acapacitance value of the N-type variable capacitance C12 is decreased.On the other hand, in the case in which the gate electrode VG is higherthan 0 V, the depletion layer 148 is reduced in the N well region 121provided under the gate electrode 143 as shown in FIG. 40 so that thecapacitance value of the N-type variable capacitance C12 is increased.Thus, it is possible to variably set the capacitance value of the N-typevariable capacitance C12 based on the gate voltage VG to be applied tothe gate electrode 143. Also in the P-type variable capacitance C11,similarly, it is possible to change the capacitance value based on thegate voltage to be applied to the gate electrode 133.

[0026] However, when the pocket injecting process shown in FIG. 36 isexecuted in order to enhance a short channel characteristic (to suppressthe short channel effect), pocket regions of a reverse conductivity typeto that of the body region are formed with the accumulation typevariable capacitance in extraction electrode regions and the body regionto be a region of the semiconductor substrate 101 which is provided justbelow the gate electrode. Therefore, there has been a problem in that aseries resistance is increased.

[0027]FIG. 41 is a circuit diagram showing an equivalent circuit of thevariable capacitance in FIG. 38. As shown in FIG. 41, the variablecapacitance is equivalently represented by a series connection of acapacitance component C10 and a resistance component R10.

[0028] On the other hand, an index representing an electricalcharacteristic of the variable capacitance includes a Q-factor(Q-value). The Q-value is expressed in the following equation (1),wherein Q represents a Q-value, ω represents an angular frequency, Crepresents a capacitance value of the capacitance component C10 and Rrepresents a resistance value of the resistance component R10.[Equation  1] $\begin{matrix}{Q = \frac{1}{\omega \quad {CR}}} & (1)\end{matrix}$

[0029] When the Q-value is increased, an energy efficiency of thecapacitance is enhanced. There has been a problem in that the resistancevalue R of the resistance component R10 is increased by the presence ofthe pocket regions so that the Q-value is decreased in accordance withthe equation (1).

SUMMARY OF THE INVENTION

[0030] It is an object of the present invention to obtain asemiconductor device having such a structure that respective electricalcharacteristics of an insulated gate type transistor and an insulatedgate type capacitance are not deteriorated and a method of manufacturingthe semiconductor device.

[0031] A first aspect of the present invention, a semiconductor deviceincludes an insulated gate type transistor and an insulated gate typecapacitance which are formed in a semiconductor substrate. The insulatedgate type transistor includes a gate insulating film, a gate electrodeand source-drain regions. The gate insulating film for a transistor isselectively formed on the semiconductor substrate. The gate electrodefor a transistor is formed on the gate insulating film for a transistor.The source-drain regions are formed to interpose a body region for atransistor provided under the gate electrode for a transistor in asurface of the semiconductor substrate. The insulated gate typecapacitance includes a gate insulating film, a gate electrode andextraction electrode regions. The gate insulating film for a capacitanceis selectively formed on the semiconductor substrate. The gate electrodefor a capacitance is formed on the gate insulating film for acapacitance. The extraction electrode regions are formed to interpose abody region for a capacitance provided under the gate electrode for acapacitance in the surface of the semiconductor substrate. The insulatedgate type transistor has pocket regions for a transistor of a reverseconductivity type to that of the source-drain regions formed from thesource-drain regions to a part of the body region for a transistor. Theinsulated gate type capacitance has no region of a reverse conductivitytype to that of the extraction electrode regions in a vicinal region ofthe extraction electrode regions in the body region side for acapacitance.

[0032] The insulated gate type transistor of the semiconductor devicehas the pocket regions for a transistor. Consequently, a short channeleffect can be suppressed.

[0033] On the other hand, the insulated gate type capacitance does nothave the region of the reverse conductivity type to that of theextraction electrode regions (a region of a reverse conductivity typewhich is adjacent to the extraction electrode regions) in the vicinalregion of the extraction electrode regions on the body region side for acapacitance. Therefore, an electrical characteristic can be preventedfrom being deteriorated by the presence of the region of a reverseconductivity type which is adjacent to the extraction electrode regions.

[0034] As a result, it is possible to obtain a semiconductor devicehaving such a structure that the respective electrical characteristicsof the insulated gate type transistor and the insulated gate typecapacitance are not deteriorated.

[0035] A second aspect of the present invention, a semiconductor deviceincludes an insulated gate type transistor and an insulated gate typecapacitance which are formed in a semiconductor substrate. The insulatedgate type transistor includes a gate insulating film, a gate electrode,source-drain regions and pocket regions. The gate insulating film for atransistor is selectively formed on the semiconductor substrate. Thegate electrode for a transistor is formed on the gate insulating filmfor a transistor. The source-drain regions are formed to interpose abody region for a transistor provided under the gate electrode for atransistor in a surface of the semiconductor substrate. The pocketregions for a transistor of a reverse conductivity type to that of thesource-drain regions are formed from the source-drain regions to a partof the body region for a transistor. The insulated gate type capacitanceincludes a gate insulating film, a gate electrode, extraction electroderegions and pocket regions. The gate insulating film for a capacitanceis selectively formed on the semiconductor substrate. The gate electrodefor a capacitance is formed on the gate insulating film for acapacitance. The extraction electrode regions are formed to interpose abody region for a capacitance provided under the gate electrode for acapacitance in the surface of the semiconductor substrate. The pocketregions for a capacitance of a reverse conductivity type to that of theextraction electrode regions are formed from the extraction electroderegions to a part of the body region for a capacitance. An impurityconcentration in a surface of the body region for a capacitance isdifferent from that in a surface of the body region for a transistor.

[0036] The impurity concentration in the surface of the body region fora capacitance and the impurity concentration in the surface of the bodyregion for a transistor are set to be different from each other.Therefore, it is possible to enhance a degree of freedom of a design inthe device.

[0037] These and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0038]FIG. 1 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to afirst embodiment of the present invention,

[0039] FIGS. 2 to 7 are sectional views showing a method ofmanufacturing the semiconductor device according to the firstembodiment,

[0040]FIG. 8 is a sectional view showing a structure of a semiconductordevice according to a second embodiment of the present invention,

[0041]FIG. 9 is a view illustrating the influence of a high frequencycurrent of an N-type variable capacitance according to the secondembodiment,

[0042]FIG. 10 is a view illustrating the influence of a high frequencycurrent of an N-type variable capacitance having pocket regions formedin an SOI substrate,

[0043]FIG. 11 is a sectional view showing a structure of a semiconductordevice according to a third embodiment of the present invention,

[0044] FIGS. 12 to 15 are sectional views showing a method ofmanufacturing a semiconductor device according to a fourth embodiment,

[0045]FIG. 16 is a sectional view showing a structure of a semiconductordevice according to a fifth embodiment of the present invention,

[0046]FIG. 17 is a sectional view showing a structure of a semiconductordevice according to a sixth embodiment of the present invention,

[0047]FIG. 18 is a diagram illustrating a layout structure of asemiconductor device according to a seventh embodiment of the presentinvention,

[0048]FIG. 19 is a sectional view showing a structure of a high voltagetransistor formation region and a variable capacitance formation regionin the semiconductor device according to the seventh embodiment,

[0049]FIG. 20 is a sectional view showing a structure of a semiconductordevice according to an eighth embodiment of the present invention,

[0050]FIG. 21 is a sectional view showing a part of a method ofmanufacturing a semiconductor device having a MOS transistor and avariable capacitance according to a ninth embodiment of the presentinvention,

[0051] FIGS. 22 to 26 are sectional views showing a method ofmanufacturing an N-type variable capacitance in a semiconductor deviceaccording to a tenth embodiment,

[0052]FIG. 27 is a sectional view showing a structure of a semiconductordevice according to an eleventh embodiment of the present invention,

[0053]FIG. 28 is a sectional view showing a structure of a first mode ofa semiconductor device according to a twelfth embodiment of the presentinvention,

[0054]FIG. 29 is a sectional view showing a structure of a second modeof the semiconductor device according to the twelfth embodiment of thepresent invention,

[0055]FIG. 30 is a sectional view showing a structure of a first mode ofa semiconductor device according to a thirteenth embodiment of thepresent invention,

[0056] FIGS. 31 to 35 are sectional views showing a method of forming aporous silicon layer,

[0057]FIGS. 36 and 37 are sectional views showing a method ofmanufacturing a MOS transistor having pocket regions according to aconventional example,

[0058]FIG. 38 is a sectional view showing a structure of a variablecapacitance,

[0059]FIGS. 39 and 40 are views illustrating a capacitance value settingoperation for a variable capacitance, and

[0060]FIG. 41 is a circuit diagram showing an equivalent circuit of thevariable capacitance illustrated in FIG. 38.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] <First Embodiment>

[0062]FIG. 1 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to afirst embodiment of the present invention.

[0063] As shown in FIG. 1, an NMOS transistor Q1, a PMOS transistor Q2,an N-type variable capacitance C1 and a P-type variable capacitance C2are formed in an NMOS formation region A1, a PMOS formation region A2,an N-type variable capacitance formation region A3 and a P-type variablecapacitance formation region A4, respectively. Each of the formationregions A1 to A4 is isolated by an isolating film (not shown) or thelike. Moreover, well regions 11, 21, 31 and 41 to be body regions areformed in the formation regions A1, A2, A3 and A4, respectively.

[0064] In the NMOS formation region A1, a gate oxide film 12 isselectively formed on a surface of the P well region 11 and an N⁺-typegate electrode 13 is formed on the gate oxide film 12. N⁺ source-drainregions 14 and 14 are formed to interpose a channel region to be asurface region of the P well region 11 provided under the gate electrode13, and tip regions protruded and opposed to each other between the N⁺source-drain regions 14 and 14 are extension portions 14 e,respectively.

[0065] In a vicinal region of the extension portion 14 e, P⁻ pocketregions 17 are formed from the extension portion 14 e to a part of thechannel region. Moreover, side walls 16 and 16 are formed on both sidesurfaces of the gate electrode 13, respectively. Furthermore, a silicideregion 14 s and a silicide region 13 s are formed in a surface of the N⁺source-drain regions 14 and an upper layer portion of the gate electrode13, respectively.

[0066] Thus, the NMOS transistor Q1 is formed by the gate oxide film 12,the gate electrode 13, the N⁺ source-drain regions 14, the side wall 16and the P⁻ pocket regions 17.

[0067] In the PMOS formation region A2, a gate oxide film 22 isselectively formed on a surface of the N well region 21 and a P⁺-typegate electrode 23 is formed on the gate oxide film 22. P⁺ source-drainregions 24 and 24 are formed to interpose a channel region providedunder the gate electrode 23, and tip regions protruded and opposed toeach other between the P⁺ source-drain regions 24 and 24 are extensionportions 24 e, respectively.

[0068] In a vicinal region of the extension portion 24 e, N⁻ pocketregions 27 are formed from the extension portion 24 e to a part of thechannel region. Moreover, side walls 26 and 26 are formed on both sidesurfaces of the gate electrode 23, respectively. Furthermore, a silicideregion 24 s and a silicide region 23 s are formed in a surface of the P⁺source-drain regions 24 and an upper layer portion of the gate electrode23, respectively.

[0069] Thus, a PMOS transistor Q2 is formed by the gate oxide film 22,the gate electrode 23, the P⁺ source-drain regions 24, the side wall 26and the N⁻ pocket regions 27.

[0070] In the N-type variable capacitance formation region A3, a gateoxide film 32 is selectively formed on a surface of the N well region 31and an N⁺-type gate electrode 33 is formed on the gate oxide film 32. N⁺extraction electrode regions 34 and 34 are formed to interpose a bodysurface region to be a surface of the N well region 31 provided underthe gate electrode 33. Tip regions protruded and opposed to each otherbetween the N⁺ extraction electrode regions 34 and 34 are extensionportions 34 e, respectively.

[0071] Moreover, side walls 36 and 36 are formed on both side surfacesof the gate electrode 33, respectively. Furthermore, a silicide region34 s and a silicide region 33 s are formed in a surface of the N⁺extraction electrode regions 34 and an upper layer portion of the gateelectrode 33, respectively.

[0072] Thus, an N-type (N⁺ gate/N⁻ body type) variable capacitance C1 isformed by the gate oxide film 32, the gate electrode 33, the N⁺extraction electrode regions 34 and the side wall 36. More specifically,the N-type variable capacitance C1 becomes an insulated gate typecapacitance in which the N⁺ extraction electrode regions 34 are set toone of electrodes, the gate electrode 33 is set to the other electrodeand the gate oxide film 32 is set to an interelectrode insulating film.By a gate voltage to be applied to the gate electrode 33, it is possibleto variably set a capacitance value by changing the extension of adepletion layer in the N well region 31 provided under the gateelectrode 33.

[0073] In the P-type variable capacitance formation region A4, a gateoxide film 42 is selectively formed on a surface of the P well region 41and a P⁺-type gate electrode 43 is formed on the gate oxide film 42. P⁺extraction electrode regions 44 and 44 are formed to interpose a bodysurface region provided under the gate electrode 43. Tip regionsprotruded and opposed to each other between the P⁺ extraction electroderegions 44 and 44 are extension portions 44 e, respectively.

[0074] Moreover, side walls 46 and 46 are formed on both side surfacesof the gate electrode 43, respectively. Furthermore, a silicide region44 s and a silicide region 43 s are formed in a surface of the P⁺extraction electrode region 44 and an upper layer portion of the gateelectrode 43, respectively.

[0075] Thus, a P-type (P⁺ gate/P⁻ body type) variable capacitance C2 isformed by the gate oxide film 42, the gate electrode 43, the P⁺extraction electrode regions 44 and the side wall 46. More specifically,the P-type variable capacitance C2 becomes an insulated gate typecapacitance in which the P⁺ extraction electrode regions 44 are set toone of electrodes, the gate electrode 43 is set to the other electrodeand the gate oxide film 42 is set to an interelectrode insulating film.By a gate voltage to be applied to the gate electrode 43, it is possibleto variably set a capacitance value by changing the extension of adepletion layer in the P well region 41 provided under the gateelectrode 43.

[0076] As described above, in the semiconductor device according to thefirst embodiment, the pocket regions are present in the MOS transistor.Therefore, it is possible to obtain a MOS transistor in which a shortchannel effect is suppressed.

[0077] On the other hand, pocket regions (regions of a reverseconductivity type which are adjacent to extraction electrode regions)are not present in the variable capacitance. More specifically, theregion of a reverse conductivity type to that of the extractionelectrode regions is not present at all in a region provided in thevicinity of the extraction electrode regions of the variablecapacitance. Therefore, a series resistance is low and a Q-value is notdeteriorated.

[0078] As the semiconductor device according to the first embodiment,thus, it is possible to obtain a semiconductor device comprising a MOStransistor suppressing a short channel effect and a variable capacitancein which a series resistance is low and a Q-value is not deteriorated.

[0079] FIGS. 2 to 7 are sectional views showing a method ofmanufacturing the semiconductor device according to the firstembodiment. A procedure for manufacturing the semiconductor deviceaccording to the first embodiment will be described below with referenceto these drawings.

[0080] As shown in FIG. 2, first of all, a P well region 11, an N wellregion 21, an N well region 31 and a P well region 41 which are to bebody regions are formed, by an existing method, in an NMOS formationregion A1, a PMOS formation region A2, an N-type variable capacitanceformation region A3 and a P-type variable capacitance formation regionA4 which are isolated from each other. Then, a gate oxide film 12 and anN⁺-type gate electrode 13 are selectively formed on a surface of the Pwell region 11, a gate oxide film 22 and a P⁺-type gate electrode 23 areselectively formed on a surface of the N well region 21, a gate oxidefilm 32 and an N⁺-type gate electrode 33 are selectively formed on asurface of the N well region 31, and a gate oxide film 42 and a P⁺-typegate electrode 43 are selectively formed on a surface of the P wellregion 41.

[0081] As shown in FIG. 3, a resist 51 is formed on a region other thanthe NMOS formation region A1, and a P-type impurity ion 61 and an N-typeimpurity ion 62 are then implanted and diffused sequentially into onlythe NMOS formation region A1 by varying an implantation energy with thegate electrode 13 to be a mask. Thus, a P⁻ diffusion region 19 and an N⁻extension region 18 are formed, respectively.

[0082] As a specific example of the implantation of the N-type impurityion 62, it can be proposed that an arsenic ion is implanted at animplantation energy of 3 to 20 keV, a dose of 1×10¹⁴ to 1×10¹⁵/cm², andan implantation angle of 0 degree.

[0083] As a specific example of the implantation of the P-type impurityion 61, moreover, it can be proposed that a boron ion is implanted at animplantation energy of 10 to 20 keV, a dose of 1×10¹³ to 3×10¹³/cm², andan implantation angle of 0 to 45 degrees.

[0084] As shown in FIG. 4, subsequently, the resist 51 is removed and aresist 52 is then formed on a region other than the N-type variablecapacitance formation region A3 and an N-type impurity ion 63 isthereafter implanted into only the N-type variable capacitance formationregion A3 with the same contents as those of the implantation of theN-type impurity ion 62, for example. Consequently, an N⁻ extensionregion 38 is formed. In this case, it can also be proposed that anN-type impurity ion is implanted on the same conditions as those of anN-type impurity ion 64 which will be described below, thereby furtherforming N⁻ pocket regions.

[0085] As shown in FIG. 5, next, the resist 52 is removed and a resist53 is then formed on a region other than the PMOS formation region A2,and the N-type impurity ion 64 and a P-type impurity ion 65 are thenimplanted and diffused sequentially into only the PMOS formation regionA2 by varying an implantation energy with the gate electrode 23 to be amask. Thus, an N⁻ diffusion region 29 and a P⁻ extension region 28 areformed.

[0086] As a specific example of the implantation of the P-type impurityion 65, moreover, it can be proposed that a BF₂ ion is implanted at animplantation energy of 3 to 10 keV, a dose of 1×10¹⁴ to 1×10¹⁵/cm², andan implantation angle of 0 degree.

[0087] As a specific example of the implantation of the N-type impurityion 64, furthermore, it can be proposed that an arsenic ion is implantedat an implantation energy of 50 to 150 keV, a dose of 1×10¹³ to3×10¹³/cm², and an implantation angle of 0 to 45 degrees.

[0088] As shown in FIG. 6, subsequently, the resist 53 is removed and aresist 54 is then formed on a region other than the P-type variablecapacitance formation region A4 and a P-type impurity ion 66 isthereafter implanted into only the P-type variable capacitance formationregion A4 with the same contents as those of the implantation of theP-type impurity ion 65, for example. Consequently, a P⁻ extension region48 is formed. In this case, it can also be proposed that a P-typeimpurity ion is implanted on the same conditions as those of the P-typeimpurity ion 61 to further form P⁻ pocket regions.

[0089] When the resist 54 is removed as shown in FIG. 7, it is possibleto obtain such a structure that a P⁻ diffusion region 19 and an N⁻diffusion region 29 which are to be pocket regions are present in onlythe MOS transistor formation regions A1 and A2 and a diffusion region tobe the pocket regions is not present in the variable capacitanceformation regions A3 and A4.

[0090] Subsequently, the structure shown in FIG. 1 can be obtained byusing an existing method of forming a MOS transistor and a variablecapacitance. In the structure shown in FIG. 1, a side wall is formed andsource-drain regions (extraction electrode regions) are then formed, andfurthermore, the inside of a surface of the source-drain regions(extraction electrode regions) and an upper layer portion of the gateelectrode are silicided by a self-align silicide (salicide) process,thereby forming a silicide region and reducing a resistance.

[0091] As a specific example of the formation of the N⁺ source-drainregions 14 of the NMOS transistor Q1, it can be proposed that an arsenicion is implanted at an implantation energy of 20 to 70 keV, a dose of1×10¹⁵ to 1×10¹⁶/cm², and an implantation angle of 0 to 30 degrees.

[0092] As a specific example of the formation of the P⁺ source-drainregions 24 of the PMOS transistor Q2, moreover, it can be proposed thata BF₂ ion is implanted at an implantation energy of 10 to 30 keV, a doseof 1×10¹⁵ to 1×10¹⁶/cm², and an implantation angle of 0 to 30 degrees.

[0093] For example, CoSi₂, TiSi₂, NiSi₂ or the like is used for thesilicide.

[0094] While both of the N- and P-type variable capacitances are formedin the present embodiment, only one of the variable capacitances may beformed. It is preferable that a variable capacitance of such a type asto be convenient for a circuit should be formed, and the N-type variablecapacitance has a low resistance value of a series resistance componentof a body portion and a great Q-value. In this respect, the N-typevariable capacitance is more excellent.

[0095] <Second Embodiment>

[0096]FIG. 8 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to asecond embodiment of the present invention.

[0097] As shown in FIG. 8, a buried oxide film 4 is formed on a supportsubstrate 3, and an SOI layer 5 formed on the buried oxide film 4 isisolated into an NMOS formation region A1, a PMOS formation region A2,an N-type variable capacitance formation region A3 and a P-type variablecapacitance formation region A4 through an isolating film (not shown) orthe like.

[0098] An NMOS transistor Q1, a PMOS transistor Q2, an N-type variablecapacitance C1 and a P-type variable capacitance C2 which have the samestructures as those of the first embodiment are formed in the NMOSformation region A1, the PMOS formation region A2, the N-type variablecapacitance formation region A3 and the P-type variable capacitanceformation region A4, respectively.

[0099] In the semiconductor device according to the second embodiment,thus, the MOS transistors Q1 and Q2 and the variable capacitances C1 andC2 which are similar to those of the first embodiment are formed on theSOI substrate (the support substrate 3, the buried oxide film 4 and theSOI layer 5). Accordingly, the structure and manufacturing method arethe same as those in the first embodiment except that a bulk substrateis replaced with the SOI substrate.

[0100]FIG. 9 is a view illustrating the influence of a high frequencycurrent of the N-type variable capacitance according to the secondembodiment. As shown in FIG. 9, a high frequency current path CP1 mainlyflows in the N-type variable capacitance C1 between N⁺ extractionelectrode regions 34 in the vicinity of a gate oxide film 32 and a gateelectrode 33. Therefore, a variable capacitance characteristic is notgreatly deteriorated.

[0101]FIG. 10 is a view illustrating the influence of a high frequencycurrent of an N-type variable capacitance having pocket regions formedin the SOI substrate. As shown in FIG. 10, a thickness of the SOI layer5 is smaller than that of the bulk substrate so that a part (shown in adotted line) of a high frequency current path CP2 flowing in an N-typevariable capacitance C1P is made invalid and a series resistance isincreased. Consequently, a degree of deterioration is great.

[0102] Thus, when P⁻ pocket regions 37 are present, the bad influence ofthe high frequency current path CP2 is increased. For the SOI structure,therefore, the structure according to the second embodiment in which thepocket regions are not provided in the variable capacitance is veryeffective.

[0103] <Third Embodiment>

[0104]FIG. 11 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to athird embodiment of the present invention.

[0105] As shown in FIG. 11, variable capacitances C3 and C4 of aninversion type are provided in place of the variable capacitances C1 andC2 of an accumulation type. More specifically, the structure accordingto the third embodiment is different from the structure according to thefirst embodiment shown in FIG. 1 in that a P well region 30 is providedin place of the N well region 31 and an N well region 40 is provided inplace of the P well region 41.

[0106] More specifically, the N-type (N⁺ gate/P⁻ body/N⁺S/D type)variable capacitance C3 and the P-type (P⁺ gate/N⁻ body/P⁺S/D type)variable capacitance C4 have structures equivalent to the structures ofthe NMOS transistor and the PMOS transistor, and are different from theNMOS transistor Q1 and the PMOS transistor Q2 in that pocket regionscorresponding to the P⁻ pocket regions 17 and 27 are not provided.

[0107] In the variable capacitance having the inversion type structure,the pocket regions and the body region (the P well region 30, the N wellregion 40) have the same conductivity types even if the pocket regionsare provided. Differently from the variable capacitance of theaccumulation type, therefore, a resistance value of a series resistancecomponent of the body region is not increased.

[0108] However, when the pocket regions are formed, an impurityconcentration distribution in a direction of a channel length becomesnonuniform. Therefore, there is a problem in that a distribution in adirection of a channel is generated on a threshold voltage for a MOStransistor and it is hard to estimate a capacitance value of thevariable capacitance based on a gate voltage.

[0109] By the structure according to the third embodiment in which thepocket regions are not provided in the variable capacitance of theinversion type, accordingly, it is possible to obtain an effect thatprecision in estimation of the capacitance value of the variablecapacitance can be enhanced.

[0110] <Fourth Embodiment>

[0111] A fourth embodiment provides a method of manufacturing asemiconductor device which is different from the method of obtaining thestructure according to the first embodiment. While the steps of formingthe extension regions of the MOS transistor and the variable capacitanceare carried out independently in the manufacturing method according tothe first embodiment, a plurality of extension regions can be formed atthe same time on the same conditions in the fourth embodiment.

[0112] FIGS. 12 to 15 are sectional views showing the method ofmanufacturing a semiconductor device according to the fourth embodiment.With reference to these drawings, description will be given to aprocedure for manufacturing a semiconductor device according to thefourth embodiment.

[0113] First of all, the structure shown in FIG. 2 is obtained in thesame manner as in the first embodiment. As shown in FIG. 12, then, aresist 55 is formed on a region other than an NMOS formation region A1and an N-type variable capacitance formation region A3, and an N-typeimpurity ion 67 is thereafter implanted into only the NMOS formationregion A1 and the N-type variable capacitance formation region A3 byusing a gate electrode 13 and a gate electrode 33 as masks.Consequently, an N⁻ extension region 18 and an N⁻ extension region 38are obtained at the same time. The N-type impurity ion 67 is implantedat an implantation angle of “0”.

[0114] As shown in FIG. 13, subsequently, a resist 56 is formed on aregion other than the NMOS formation region A1 and a P-type impurity ion68 is then implanted and diffused into only the NMOS formation region A1by using the gate electrode 13 as a mask. Consequently, a P⁻ diffusionregion 19 is formed. The P-type impurity ion 68 is obliquely implantedat a higher implantation energy than that of the N-type impurity ion 67.

[0115] As shown in FIG. 14, then, a resist 57 is formed on a regionother than a PMOS formation region A2 and a P-type variable capacitanceformation region A4, and a P-type impurity ion 69 is thereafterimplanted into only the PMOS formation region A2 and the P-type variablecapacitance formation region A4 by using a gate electrode 23 and a gateelectrode 43 as masks. Consequently, a P⁻ extension region 28 and a P⁻extension region 48 are obtained at the same time. The P-type impurityion 69 is implanted at an implantation angle of “0”.

[0116] As shown in FIG. 15, subsequently, a resist 58 is formed on aregion other than the PMOS formation region A2 and an N-type impurityion 70 is then implanted and diffused into only the PMOS formationregion A2 by using the gate electrode 23 as a mask. Consequently, an N⁻diffusion region 29 is formed. The N-type impurity ion 70 is obliquelyimplanted at a higher implantation energy than that of the P-typeimpurity ion 69.

[0117] Subsequently, it is possible to obtain the structure shown inFIG. 1 by using the existing method of forming a MOS transistor and avariable capacitance.

[0118] In the method of manufacturing a semiconductor device accordingto the fourth embodiment, thus, the extension region is simultaneouslyformed in the MOS transistor and the variable capacitance which have thesame conductivity type. As compared with the method of manufacturing asemiconductor device according to the first embodiment, therefore, twoion implanting steps can be eliminated.

[0119] <Fifth Embodiment>

[0120]FIG. 16 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to afifth embodiment of the present invention.

[0121] As shown in FIG. 16, variable capacitances C5 and C6 having noextension region are provided in place of the variable capacitances C1and C2 having the extension regions. More specifically, as compared withthe structure according to the first embodiment shown in FIG. 1, the N⁺extraction electrode regions 34 having the extension portion 34 e isreplaced with an N⁺ extraction electrode regions 35 having no extensionportion and the P⁺ extraction electrode regions 44 having the extensionportion 44 e is replaced with a P⁺ extraction electrode regions 45having no extension portion. Other structures are the same as those ofthe first embodiment shown in FIG. 1.

[0122] A method of manufacturing a semiconductor device according to thefifth embodiment is different from the method of manufacturing asemiconductor device according to the first embodiment in that the stepsof manufacturing the N⁻ extension region 38 and the P⁻ extension region48 shown in FIGS. 4 and 6 are omitted.

[0123] In the method of manufacturing a semiconductor device accordingto the fifth embodiment, thus, the step of forming the extension regionof a variable capacitance is omitted. Consequently, two steps, that is,the step of forming a resist and the step of implanting an ion can beeliminated as compared with the method of manufacturing a semiconductordevice according to the first embodiment.

[0124] Although the variable capacitance cannot produce the effect bythe provision of the extension portion in the semiconductor deviceaccording to the fifth embodiment, the effect of providing no pocketregion can be obtained in the same manner as that in each of the firstto fourth embodiments.

[0125] <Sixth Embodiment>

[0126]FIG. 17 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to asixth embodiment of the present invention.

[0127] As shown in FIG. 17, variable capacitances C7 and C8 havingextension regions in higher concentrations than those of the variablecapacitances C1 and C2 are provided in place of the variablecapacitances C1 and C2.

[0128] More specifically, as compared with the structure according tothe first embodiment, the N⁻ extension region 38 and the P⁻ extensionregion 48 shown in FIGS. 4 and 6 are formed to have impurityconcentrations which are approximately twice to 100 times as high asthose of the N⁻ extension region 18 and the P⁻ extension region 28 inthe MOS transistor.

[0129] Although gate lengths of MOS transistors Q1 and Q2 are almostequal to those of the variable capacitances C7 and C8 in FIG. 17, thegate length of the variable capacitance is actually set to be greaterthan that of the MOS transistor in many cases.

[0130] Accordingly, the influence of a short channel effect in thevariable capacitance is smaller than that in the MOS transistor.Consequently, a bad effect is lessened with an increase in the impurityconcentration of the extension region. To the contrary, it is possibleto obtain a greater advantage that a series resistance component of thevariable capacitance can be reduced with the increase in the impurityconcentration of the extension region.

[0131] While the example in which the extension region is formed in ahigh concentration has been described in the present embodiment, thesame effects can be obtained even if an implantation energy of animpurity ion is increased to be approximately 1.2 to 30 times as high asthat of the MOS transistor and a depth of the extension region isincreased to be approximately 1.2 to 30 times as great as that of theMOS transistor.

[0132] <Seventh Embodiment>

[0133] In general, if a device is subjected to scaling, a power supplyvoltage is also subjected to the scaling and is thereby reduced.Consequently, it is necessary to provide an interface with another chip(device) to be operated at a high voltage.

[0134] At this time, it is necessary to fabricate a 3.3 V or 5.0 Vcompatible MOS transistor for a high voltage (hereinafter referred to asa “transistor for a high voltage”), for example, in addition to a highperformance MOS transistor (hereinafter referred to as a “highperformance transistor”) which is subjected to the scaling in thedevice.

[0135] By a comparison of the transistor for a high voltage with thehigh performance transistor, a gate length is greater and a gate oxidefilm has a greater thickness, and furthermore, an extension region isformed on different conditions and pocket regions are not formed in manycases. The extension region is formed on the different conditions inorder to increase a hot carrier tolerance such that an S/D breakdownphenomenon such as punch-through is not presented at a high voltage. Thepocket regions do not need to be formed because the gate length isgreat.

[0136]FIG. 18 is a diagram illustrating a layout structure of asemiconductor device having a MOS transistor and a variable capacitanceaccording to a seventh embodiment of the present invention. As shown inFIG. 18, the semiconductor device is constituted by a high performancetransistor formation region E1, a high voltage transistor formationregion E2 and a variable capacitance formation region E3 according tothe seventh embodiment, and a high performance transistor, a transistorfor a high voltage and a variable capacitance are provided in theformation regions E1 to E3, respectively.

[0137]FIG. 19 is a sectional view showing structures of the high voltagetransistor formation region E2 and the variable capacitance formationregion E3 in the semiconductor device according to the seventhembodiment.

[0138] In an NMOS formation region A5 of the high voltage transistorformation region E2, a gate oxide film 72 is selectively formed on asurface of a P well region 71 to be a body region and an N⁺-type gateelectrode 73 is formed on the gate oxide film 72. N⁺ source-drainregions 74 and 74 are formed to interpose a channel region providedunder the gate electrode 73 and tip regions opposed to each otherbetween the N⁺ source-drain regions 74 and 74 are extension portions 74e, respectively.

[0139] Moreover, side walls 76 and 76 are formed on both side surfacesof the gate electrode 73, respectively. Furthermore, a silicide region74 s and a silicide region 73 s are formed in a surface of the N⁺source-drain regions 74 and an upper layer portion of the gate electrode73, respectively.

[0140] Thus, an NMOS transistor Q3 for a high voltage is formed by thegate oxide film 72, the gate electrode 73, the N⁺ source-drain regions74 and the side wall 76.

[0141] In a PMOS formation region A6 of the high voltage transistorformation region E2, a gate oxide film 82 is selectively formed on asurface of an N well region 81 and a P⁺-type gate electrode 83 is formedon the gate oxide film 82. P⁺ source-drain regions 84 and 84 are formedto interpose a channel region provided under the gate electrode 83 andtip regions opposed to each other between the P⁺ source-drain regions 84and 84 are extension portions 84 e, respectively.

[0142] Moreover, side walls 86 and 86 are formed on both side surfacesof the gate electrode 83, respectively. Furthermore, a silicide region84 s and a silicide region 83 s are formed in a surface of the P⁺source-drain regions 84 and an upper layer portion of the gate electrode83, respectively.

[0143] Thus, a PMOS transistor Q4 for a high voltage is formed by thegate oxide film 82, the gate electrode 83, the P⁺ source-drain regions84 and the side wall 86.

[0144] The high performance transistor formed in the high performancetransistor formation region E1 is provided to have the same structure asthat of each of the NMOS transistor Q1 and the PMOS transistor Q2according to the first embodiment shown in FIG. 1, for example, which isnot shown in FIG. 19.

[0145] The NMOS transistor Q3 for a high voltage and the PMOS transistorQ4 for a high voltage are different from the NMOS transistor Q1 and thePMOS transistor Q2 for a high performance in that gate lengths aregreater, the gate oxide films have greater thicknesses, the extensionregions are set on different conditions and the pocket regions are notformed.

[0146] On the other hand, an N-type variable capacitance C1 and a P-typevariable capacitance C2 are formed in an N-type variable capacitanceformation region A3 and a P-type variable capacitance formation regionA4 in the variable capacitance formation region E3, respectively.

[0147] The N-type variable capacitance C1 and the P-type variablecapacitance C2 have the same basic structures as those of the N-typevariable capacitance C1 and the P-type variable capacitance C2 accordingto the first embodiment shown in FIG. 1.

[0148] In each of the N-type variable capacitance C1 and the P-typevariable capacitance C2, an extension region is formed to have a higherimpurity concentration than that of the extension region of each of theNMOS transistor Q1 and the PMOS transistor Q2 and an equal gate lengthon the same conditions (at least the impurity concentration is almostequal) as compared with the NMOS transistor Q3 for a high voltage andthe PMOS transistor Q4 for a high voltage. In the N-type variablecapacitance C1 and the P-type variable capacitance C2, moreover, thegate oxide films have equal thicknesses as compared with the NMOStransistor Q1 and the PMOS transistor Q2.

[0149] In the semiconductor device having such a structure according tothe seventh embodiment, the extension regions in the NMOS transistor Q3for a high voltage and the N-type variable capacitance C1 can be formedat the same step and the extension regions of the PMOS transistor Q4 fora high voltage and the P-type variable capacitance C2 can be formed atthe same step. Therefore, it is possible to obtain a semiconductordevice having a variable capacitance with a series resistance componentreduced while minimizing the number of manufacturing steps.

[0150] In some cases, moreover, the extension region of the transistorfor a high voltage is to be formed as an LDD region to have an impurityconcentration which is almost equal to that of the extension region ofthe high performance transistor. In these cases, an implantation energyis increased and the extension region is formed deeply.

[0151] Accordingly, it is possible to obtain the same effects, as thosein the semiconductor device according to the sixth embodiment by formingthe extension region of the variable capacitance comparatively deeply onthe same conditions as those of the extension region of the transistorfor a high voltage.

[0152] <Eighth Embodiment>

[0153] An eighth embodiment provides a semiconductor device having sucha structure as to comprise a MOS transistor and a variable capacitancein which channel regions have different impurity concentrations,respectively. In the semiconductor device according to the eighthembodiment, the impurity concentrations of the channel regions in theMOS transistor and the variable capacitance are set to be different fromeach other so that a degree of freedom of a design in the device can beenhanced, for example, a threshold voltage can be set separately.

[0154]FIG. 20 is a sectional view showing a structure of thesemiconductor device having the MOS transistor and the variablecapacitance according to the eighth embodiment of the present invention.In FIG. 20, a PMOS transistor Q2 to be formed in a PMOS formation regionA2 is the same as the PMOS transistor Q2 according to the firstembodiment shown in FIG. 1.

[0155] On the other hand, an N-type variable capacitance C9 to be formedin an N-type variable capacitance formation region A3 has P⁻ pocketregions 37 in the vicinity of an extension portion 34 e and an N wellregion 31 provided between N⁺ extraction electrode regions 34 and 34acts as a high concentration channel region 31 c. Other structures arethe same as the structure of the N-type variable capacitance C1according to the first embodiment shown in FIG. 1.

[0156] The N-type variable capacitance C9 includes the highconcentration channel region 31 c having a higher N-type impurityconcentration than that of other regions of the N well region 31. Thehigh concentration channel region 31 c can cancel the P⁻ pocket regions37 to sufficiently compensate for a reduction in a series resistancecomponent. Therefore, a Q-value of the variable capacitance can be fullyincreased.

[0157] In the structure shown in FIG. 20, thus, when a channelconcentration is to be changed between the PMOS transistor Q2 and theN-type variable capacitance C9, the high concentration channel region 31c is provided in the N-type variable capacitance C9, thereby increasingthe Q-value of the variable capacitance. More specifically, thestructure shown in FIG. 20 is a desirable example in which impurityconcentrations in the respective channel regions of the MOS transistorand the variable capacitance are set to be different from each other,thereby enhancing a degree of freedom of a design.

[0158] After the N well region 31 is formed, an N-type impurity isfurther implanted into an upper layer portion of the N well region 31 toobtain the high concentration channel region 31 c. More specifically, astep of forming the high concentration channel region 31 c is requiredseparately.

[0159] While only the PMOS transistor and the N-type variablecapacitance are shown in FIG. 20, it is a matter of course that an NMOStransistor and a P-type variable capacitance can also be formed to havethe same structures.

[0160] <Ninth Embodiment>

[0161]FIG. 21 is a sectional view showing a part of a method ofmanufacturing a semiconductor device having a MOS transistor and avariable capacitance according to a ninth embodiment of the presentinvention.

[0162] In the method of manufacturing a semiconductor device accordingto the ninth embodiment, pocket regions are formed in both the MOStransistor and the variable capacitance.

[0163] It is assumed that source-drain regions are formed on the MOStransistor side and extraction electrode regions 34 are formed on thevariable capacitance side by first ion implantation and diffusionthrough a forming step based on an existing method.

[0164] For the first impurity implantation and diffusion, a heattreatment (for example, RTA (Rapid Thermal Anneal) at 900 to 1100° C.for 10 to 120 seconds in an N₂ atmosphere) is carried out afterimplantation of an N-type impurity. For the heat treatment, a crystaldefect formed by the implantation of the N-type impurity is recovered.

[0165] Subsequent processings are peculiar to the manufacturing methodaccording to the ninth embodiment. In the ninth embodiment, furthermore,second impurity implantation and diffusion is not carried out over theMOS transistor but only the variable capacitance as shown in FIG. 21. Inan example of FIG. 21, for the second impurity implantation, an N-typeimpurity ion 91 is implanted by using a gate electrode 33 as a mask tocarry out a heat treatment. Consequently, N⁺ extraction electroderegions 34 h are formed so that an N-type variable capacitance C15 isfinally obtained.

[0166] Examples of the second impurity implantation and diffusioninclude annealing to be carried out at a comparatively low temperatureof 500 to 800° C. for approximately 10 to 120 minutes after theimplantation of the N-type impurity.

[0167] The second impurity implantation and diffusion is carried outover only the variable capacitance and the heat treatment is performedat the comparatively low temperature during the diffusion as describedabove. Therefore, there is presented TED (Transient Enhanced Diffusion)to be a phenomenon in which a crystal defect formed by the secondimpurity ion implantation is introduced into a well region of thevariable capacitance and a defect portion and an impurity are coupled toeach other and are greatly diffused.

[0168] By the TED phenomenon, impurities in P⁻ pocket regions 37 and theN⁺ extraction electrode regions 34 h which are formed in the N-typevariable capacitance C15 are diffused again. As a result, the presenceof the P⁻ pocket regions 37 do not have such an influence that a seriesresistance is reduced. Consequently, it is possible to obtain the N-typevariable capacitance C15 having a great Q-value.

[0169] While FIG. 21 shows the N-type variable capacitance C15, it is amatter of course that the present invention can also be applied to aP-type variable capacitance.

[0170] The second implantation may include a process of implanting animpurity ion of the N type in an oblique direction.

[0171] In this case, the deterioration in the resistance component bythe pocket regions 37 can be effectively suppressed by the ionimplantation in the oblique direction.

[0172] <Tenth Embodiment>

[0173] FIGS. 22 to 26 are sectional views showing a method ofmanufacturing an N-type variable capacitance in a semiconductor devicehaving a MOS transistor and a variable capacitance according to a tenthembodiment of the present invention. With reference to these drawings,description will be given to a procedure for manufacturing the N-typevariable capacitance according to the tenth embodiment.

[0174] As shown in FIG. 22, first of all, a lamination structure havinga gate oxide film 32, a gate electrode 33 and an oxide film 59 for amask is selectively provided on a surface of an N well region 31. Byusing the lamination structure as a mask, N- and P-type impurities areintroduced to form an N⁻ extension region 38 and a P⁻ diffusion region39, respectively. For a material of the gate electrode 33 to be formed,polysilicon is used.

[0175] As shown in FIG. 23, next, isotropic polysilicon etching iscarried out over the gate electrode 33 to partially remove a peripheralregion in a direction of a gate length of the gate electrode 33. Thus, agate electrode 33 n having a small gate length is obtained.

[0176] As shown in FIG. 24, then, wet etching for an oxide film iscarried out over the oxide film 59 for a mask and the gate oxide film32. Consequently, an oxide film 59 n for a mask and a gate oxide film 32n are obtained by reducing the oxide film 59 for a mask and the gateoxide film 32.

[0177] As shown in FIG. 25, then, a side wall 36 is formed on a sidesurface of the gate electrode 33 n.

[0178] As shown in FIG. 26, thereafter, an N-type impurity ion 75 isimplanted and diffused by using the gate electrode 33 n and the sidewall 36 as masks. Consequently, N⁺ extraction electrode regions 34 d areobtained. The N⁺ extraction electrode regions 34 d are formed in aregion including a whole P⁻ diffusion region 39 and an N-type impurityconcentration is higher than a P-type impurity concentration of the P⁻diffusion region 39. Therefore, the influence of the P⁻ diffusion region39 can be cancelled completely. More specifically, pocket regions arenot present in the finished variable capacitance.

[0179] In the tenth embodiment, thus, the side wall is formed and theextraction electrode regions are provided after the gate length of thegate electrode is reduced. Consequently, the finished device can havesuch a structure that the pocket regions are not present. Therefore, itis possible to obtain an N-type variable capacitance having a greatQ-value even if pocket regions forming step is included.

[0180] While the method of manufacturing the N-type variable capacitancehas been described in the tenth embodiment, it is a matter of coursethat a P-type variable capacitance can be manufactured in the samemanner.

[0181] <Eleventh Embodiment>

[0182]FIG. 27 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according toan eleventh embodiment of the present invention. In FIG. 27, an NMOStransistor Q1 to be formed in an NMOS formation region A1 is the same asthe NMOS transistor Q1 according to the first embodiment shown in FIG.1.

[0183] On the other hand, an N-type variable capacitance C1 w to beformed in an N-type variable capacitance formation region A3 isdifferent in that a thickness of a gate oxide film 32 w is greater thanthat of a gate oxide film 12. Other structures are the same as those ofthe N-type variable capacitance C1 according to the first embodimentshown in FIG. 1.

[0184] An oscillation frequency f of an LC type VCO is determined by thefollowing equation (2). Therefore, it is desirable that a capacitancecomponent of a variable capacitance should be reduced in order tofabricate an oscillator for oscillation at a high frequency.[Equation  2] $\begin{matrix}{f = \frac{1}{2\pi \sqrt{LC}}} & (2)\end{matrix}$

[0185] However, there is a problem in that a series parasitic resistanceis increased if a variable capacitance is manufactured in a smallpattern.

[0186] As shown in FIG. 27, when the gate oxide film 32 w is formed tohave a greater thickness than that of the gate oxide film 12, thecapacitance component of the variable capacitance can be reduced withoutchanging a pattern size, that is, increasing a parasitic resistancecomponent. Furthermore, a Q-value can also be enhanced by a reduction inthe capacitance component in accordance with the equation (1).

[0187] Moreover, in the case in which a transistor for a high voltage isprovided in addition to a high performance transistor as in thesemiconductor device according to the seventh embodiment, the gate oxidefilm 32 w is formed during formation of a gate oxide film of thetransistor for a high voltage which has a greater thickness than that ofa gate oxide film in the high performance transistor. Consequently, itis possible to obtain the gate oxide film 32 w having a smallerthickness than that of the high performance transistor withoutincreasing the number of manufacturing steps.

[0188] While only the NMOS transistor and the N-type variablecapacitance are shown in FIG. 27, it is a matter of course that a PMOStransistor and a P-type variable capacitance can also be formed to havethe same structures.

[0189] <Twelfth Embodiment>

[0190] (First Mode)

[0191]FIG. 28 is a sectional view showing a structure of a first mode ofa semiconductor device having a MOS transistor and a variablecapacitance according to a twelfth embodiment of the present invention.In FIG. 28, an NMOS transistor Q1 to be formed in an NMOS formationregion A1 is the same as the NMOS transistor Q1 according to the firstembodiment shown in FIG. 1.

[0192] On the other hand, an N-type variable capacitance C1L to beformed in an N-type variable capacitance formation region A3 isdifferent in that a material of a gate oxide film 32L has a lowerdielectric constant than that of a material of a gate oxide film 12.Other structures are the same as those of the N-type variablecapacitance C1 according to the first embodiment shown in FIG. 1.

[0193] In order to obtain the gate oxide film 32L, for example, it isproposed that F (fluorine) is implanted into only a gate oxide film 32of the N-type variable capacitance C1L.

[0194] In the first mode of the twelfth embodiment, thus, a capacitancecomponent of the variable capacitance can be reduced without increasinga parasitic resistance component. Therefore, the same effects as thosein the eleventh embodiment can be obtained.

[0195] While only the NMOS transistor and the N-type variablecapacitance are shown in FIG. 28, it is a matter of course that a PMOStransistor and a P-type variable capacitance can be formed to have thesame structures.

[0196] (Second Mode)

[0197]FIG. 29 is a sectional view showing a structure of a second modeof the semiconductor device having a MOS transistor and a variablecapacitance according to a twelfth embodiment of the present invention.In FIG. 29, an N-type variable capacitance C1 w to be formed in anN-type variable capacitance formation region A3 is different in that athickness of a gate oxide film 32 w is greater than that of a gate oxidefilm 12. Other structures are the same as those of the N-type variablecapacitance C1 according to the first embodiment shown in FIG. 1.

[0198] An NMOS transistor Q1 to be formed in an NMOS formation region A1is different in that a gate insulating film 12H is formed by using aHigh-k material having a higher dielectric constant than that of asilicon oxide film and the gate insulating film 12H is formed to have analmost equal thickness to that of the gate oxide film 32 w. Otherstructures are the same as those of the NMOS transistor Q1 according tothe first embodiment shown in FIG. 1.

[0199] Examples of the High-k material include Si₃N₄, Ta₂O₅, Al₂O₃,HfO₂, ZrO₂ and the like.

[0200] In the first mode of the twelfth embodiment, thus, it is possibleto reduce a capacitance component of the variable capacitance withoutincreasing a parasitic resistance component. Therefore, the same effectsas those in the eleventh embodiment can be obtained.

[0201] The thickness of the gate insulating film 12H is almost equal tothat of the gate oxide film 32 w. Therefore, the gate insulating film12H and the gate oxide film 32 w can be manufactured at the same step.Consequently, it is possible to obtain the gate oxide film 32 w having asmaller thickness than that of a high performance transistor withoutincreasing the number of manufacturing steps. In this case, since thegate insulating film 12H is formed of the High-k material, an electricalcharacteristic of an NMOS transistor Q1H is not adversely affected.

[0202] While only the NMOS transistor and the N-type variablecapacitance are shown in FIG. 29, it is a matter of course that a PMOStransistor and a P-type variable capacitance can be formed to have thesame structures.

[0203] <Thirteenth Embodiment>

[0204]FIG. 30 is a sectional view showing a structure of a semiconductordevice having a MOS transistor and a variable capacitance according to athirteenth embodiment of the present invention. In FIG. 30, an N-typevariable capacitance C1 p to be formed in an N-type variable capacitanceformation region A3 is different in that a porous silicon layer 8 isformed in an upper layer portion of an N well region 31. Otherstructures are the same as those of the N-type variable capacitance C1according to the first embodiment shown in FIG. 1.

[0205] By the provision of the porous silicon layer 8, an effectivedielectric constant of silicon is decreased so that a capacitancecomponent of the N-type variable capacitance C1 p can be reduced. When avacancy is continuously formed so that a rate (vacancy ratio) of thevacancy occupying the upper layer portion of the N well region 31 is toohigh, a resistance of the N well region 31 is increased. Therefore, itis desirable that the vacancy ratio should be 50% or less.

[0206] Since a capacitance component of the variable capacitance can bethus reduced without greatly increasing a parasitic resistance componentin the thirteenth embodiment, the same effects as those in the eleventhembodiment can be obtained.

[0207] While only the N-type variable capacitance is shown in FIG. 30,it is a matter of course that a P-type variable capacitance can also beformed to have the same structure.

[0208] (Formation of Porous Silicon Layer)

[0209] FIGS. 31 to 35 are sectional views showing a method of forming aporous silicon layer which has been disclosed in Japanese PatentApplication Laid-Open No. 2000-307112, for example. With reference tothese drawings, a procedure for forming the porous silicon layer will bedescribed below.

[0210] As shown in FIG. 31, first of all, a porous silicon layer 7 isformed in an upper surface of an N-type silicon substrate 6 by anodeformation. More specifically, the silicon substrate 6 is immersed in anHF solution 152 in a formation layer 151 and a current is caused to flowto the silicon substrate 6 by setting an upper platinum electrode 153 tobe a cathode and a lower platinum electrode 154 to be an anode. Forconditions, a formation time of 30 seconds and a formation currentdensity of 10 mA/cm² are set. As shown in FIG. 32, consequently, theupper surface of the silicon substrate 6 is made porous and the poroussilicon layer 7 having a thickness of approximately 0.2 μm is formed inthe upper surface of the silicon substrate 6.

[0211]FIG. 33 is a sectional view specifically showing a shape of theporous silicon layer 7. The porous silicon layer 7 has a complicatedshape as shown in FIG. 33 (more specifically, see Document 2, pp 470,FIG. 4 or Document 3, pp 379, FIG. 2 which will be described below). Inthis specification, the shape of the porous silicon layer 7 issimplified for description as shown in FIG. 32. A thickness of theporous silicon layer 7 can be controlled based on a formation time and aformation current density, and furthermore, the vacancy ratio of theporous silicon layer 7 (a density corresponding to a ratio of a siliconportion 7 a to a vacancy portion 7 b) can be controlled by aconcentration of the HF solution 152 (see SOI structure formingtechnique, pp 181 to 185, written by Seijiro Furukawa, 1987, SangyoTosho: (Document 1)).

[0212] In order to maintain stability of the porous structure of theporous silicon layer 7 for a heat treatment, next, preoxidation iscarried out at a low temperature of approximately 400° C. In order toreduce the quantity of crystal defects of an expitaxial layer 9 to beformed at a subsequent step, then, the heat treatment is carried out ata temperature of 1000° C. or more for a few seconds in a hydrogenatmosphere. Consequently, a mobility of surface atoms is dramaticallyincreased by minimization of a surface energy of the porous siliconlayer 7 and a surface hole (not shown) generated in an upper surface ofthe porous silicon layer 7 due to natural oxidation of a surface isreduced and removed. As a result, as shown in FIG. 34, a porous siliconlayer 8 is formed by sufficiently smoothening the upper surface of theporous silicon layer 7.

[0213] An upper surface of the porous silicon layer 8 maintains a singlecrystal structure of the silicon substrate 6 and has the same crystalorientation as that of the silicon substrate 6. As shown in FIG. 35, theepitaxial layer 9 having a thickness of approximately 100 nm is formedon the upper surface of the porous silicon layer 8 by an epitaxialgrowth method. See “Science of Silicon, pp 467-475, edited by TadahiroOhmi et al., REALIZE INC.” (Document 2), “IEICE TRANS. ELECTRON., VOL.E80-C, NO. 3, MARCH 1997, K. SAKAGUCHI et al., pp 378-387” (Document 3),and “Extended Abstracts of the 1998 International Conference on SolidState Devices and Materials, Hiroshima, 1998, pp 302-303” (Document 4)for the epitaxial growth of silicon on the porous silicon layer.

[0214] In the thirteenth embodiment, the porous silicon layer 8 isselectively formed in the N-type variable capacitance formation regionA3 and a P-type variable capacitance formation region A4. Thus, in thecase in which porous silicon is to be partially formed, surfaces of anNMOS formation region A1 and a PMOS formation region A2 are covered witha resist mask during the anode formation shown in FIG. 31 such that theporous silicon layer 7 is not formed.

[0215] While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

What is claimed is:
 1. A semiconductor device comprising an insulatedgate type transistor and an insulated gate type capacitance which areformed in a semiconductor substrate, said insulated gate type transistorincluding: a gate insulating film for a transistor selectively formed onsaid semiconductor substrate; a gate electrode for a transistor formedon said gate insulating film for a transistor; and source-drain regionsformed to interpose a body region for a transistor provided under saidgate electrode for a transistor in a surface of said semiconductorsubstrate, said insulated gate type capacitance including: a gateinsulating film for a capacitance selectively formed on saidsemiconductor substrate; a gate electrode for a capacitance formed onsaid gate insulating film for a capacitance; and extraction electroderegions formed to interpose a body region for a capacitance providedunder said gate electrode for a capacitance in said surface of saidsemiconductor substrate, wherein said insulated gate type transistor haspocket regions for a transistor of a reverse conductivity type to thatof said source-drain regions formed from said source-drain regions to apart of said body region for a transistor, and said insulated gate typecapacitance has no region of a reverse conductivity type to that of saidextraction electrode regions in a vicinal region of said extractionelectrode regions in said body region side for a capacitance.
 2. Thesemiconductor device according to claim 1, wherein said body region fora capacitance and said extraction electrode regions are formed to havethe same conductivity type.
 3. The semiconductor device according toclaim 1, wherein said body region for a capacitance and said extractionelectrode regions are formed to have different conductivity types fromeach other.
 4. The semiconductor device according to claim 1, whereinsaid source-drain regions include an extension portion for a transistorwhich has an upper layer portion protruded partially toward said bodyregion side for a transistor, and said extraction electrode regionsinclude an extension portion for a capacitance which has an upper layerportion protruded partially toward said body region side for acapacitance, said extension portion for a capacitance and said extensionportion for a transistor being set to have impurity concentrations equalto each other.
 5. The semiconductor device according to claim 1, whereinsaid source-drain regions include an extension portion for a transistorwhich has an upper layer portion protruded partially toward said bodyregion side for a transistor, and said extraction electrode regionsinclude no region which has an upper layer portion protruded toward saidbody region side for a capacitance.
 6. The semiconductor deviceaccording to claim 1, wherein said source-drain regions include anextension portion for a transistor which has an upper layer portionprotruded partially toward said body region side for a transistor, andsaid extraction electrode regions include an extension portion for acapacitance which has an upper layer portion protruded partially towardsaid body region side for a capacitance, said extension portion for acapacitance having a higher impurity concentration than that of saidextension portion for a transistor.
 7. The semiconductor deviceaccording to claim 1, wherein said source-drain regions include anextension portion for a transistor which has an upper layer portionprotruded partially toward said body region side for a transistor, andsaid extraction electrode regions include an extension portion for acapacitance which has an upper layer portion protruded partially towardsaid body region side for a capacitance, said extension portion for acapacitance having a greater depth than that of said extension portionfor a transistor.
 8. The semiconductor device according to claim 1,wherein said insulated gate type transistor includes first and secondtransistors, said source-drain regions of said first transistorincluding a first extension portion for a transistor which has an upperlayer portion protruded partially toward said body region side for atransistor, said source-drain regions of said second transistorincluding a second extension portion for a transistor which has an upperlayer portion protruded partially toward said body region side for atransistor, said extraction electrode regions including an extensionportion for a capacitance which has an upper layer portion protrudedpartially toward said body region side for a capacitance, and saidextension portion for a capacitance having an impurity concentration setto be almost equal to that of said second extension portion for atransistor and to be higher than that of said first extension portionfor a transistor.
 9. The semiconductor device according to claim 1,wherein said semiconductor substrate includes an SOI substrate composedof a substrate which is insulating at least in its surface and asemiconductor layer provided on the surface of said substrate.
 10. Thesemiconductor device according to claim 1, wherein said gate insulatingfilm for a capacitance has a thickness set to be greater than that ofsaid gate insulating film for a transistor.
 11. The semiconductor deviceaccording to claim 1, wherein said gate insulating film for acapacitance has a dielectric constant set to be lower than that of saidgate insulating film for a transistor.
 12. The semiconductor deviceaccording to claim 1, wherein said body region for a capacitance has avacancy portion.
 13. A semiconductor device including an insulated gatetype transistor and an insulated gate type capacitance which are formedin a semiconductor substrate, said insulated gate type transistorincluding: a gate insulating film for a transistor selectively formed onsaid semiconductor substrate; a gate electrode for a transistor formedon said gate insulating film for a transistor; source-drain regionsformed to interpose a body region for a transistor provided under saidgate electrode for a transistor in a surface of said semiconductorsubstrate; and pocket regions for a transistor of a reverse conductivitytype to that of said source-drain regions formed from said source-drainregions to a part of said body region for a transistor, said insulatedgate type capacitance includes: a gate insulating film for a capacitanceselectively formed on said semiconductor substrate; a gate electrode fora capacitance formed on said gate insulating film for a capacitance;extraction electrode regions formed to interpose a body region for acapacitance provided under said gate electrode for a capacitance in saidsurface of said semiconductor substrate; and pocket regions for acapacitance of a reverse conductivity type to that of said extractionelectrode regions, formed from said extraction electrode regions to apart of said body region for a capacitance, an impurity concentration ina surface of said body region for a capacitance being different fromthat in a surface of said body region for a transistor.
 14. Thesemiconductor device according to claim 13, wherein said impurityconcentration in said surface of said body region for a capacitance isset to be higher than that in said surface of said body region for atransistor.